Why Boundary Scan?
For the past 20+ years, access-based testing (namely In-Circuit Test or ICT) has been the workhorse in board-level test. ICT has been successfully implemented by most companies in many industries. ICT provides component-level testing and diagnostics. It has been adopted by many companies to improve manufacturing processes and to reduce cost of fault detection and repair. Changes in device packaging technology (SMT), shrinking component geometries, increasing device pin-count and disappearance of test pads has challenged the practicality of ICT in many applications. The move in most designs to operate at higher frequencies has further shortened the distances between semiconductor devices. The result has been Less Access and therefore Less Coverage! Coverage diminishes faster as access is lost In digital test. In analog test the relationship between access and coverage is more linear: Increased complexity and lack of physical access to circuits makes testing costly and time-consuming. Design for Test (DFT) is required to manage complexity, minimize test development time, and reduce overall manufacturing costs. The solution to these problems lies in the Acculogic line of Boundary Scan Test (BST) tools. Boundary Scan, formally known as IEEE/ANSI 1149.1_1190 is a standard which facilitates testing, device programming and debugging at the semiconductor, board and system levels. The standard came about as a result of the efforts of a Joint Test Action Group (JTAG) formed by several North American and European companies. IEEE Std 1149.1 was originally developed as an on-chip test infrastructure capable of extending the lifetime of available automatic test equipment (ATE). This methodology of incorporating design-for-test allows complete control and access to the boundary pins of a device without the need for a bed-of -nails or other test equipment.