ScanMaster™ is a powerful, high speed JTAG (IEEE 1149.1) controller designed for use in design verification, production test, and on-board device programming applications. Utilizing its proprietary JPCI™ bus-master with high speed cache memory behind TDI and TDO, Adaptive Clocking™ technology, and a 32-bit PCI bus architecture,
ScanMaster™ eliminates bottlenecks to data delivery. This is critical to applications like Flash programming where large amounts of data must be processed and delivered. From the exchange of data with the host computer through to delivery of vectors to targets, ScanMaster™ has been designed for high bandwidth, which enables delivery of data at speeds up to 25 Mbits/Sec.
ScanMaster™ operating environments
- High performance plug & play PCI based controller
- JPCI™ 32-bit (IEEE 1149.1) bus controller – more info.
- Fast throughput of up to 25 Mbits/sec
- 100 MHz system clock and up to 35 MHz programmable TCK rate
- Adaptive Clocking™ Technology
- 32 general purpose fully programmable parallel I/O channels – more info.
- 2 MB cache multi-page memory behind TDI/TDO – more info.
- Two 24 bit analog channels – more info.
- Performs non-compliant test access port (TAP) operations
- Meets addressable scan port (ASP) requirements
- Supports industry standard vector formats SVF, JAM/STAPL, IEEE 1532
- Programmable logic levels (1.8V to 5.0V)
- Configurable to service up to 16 individual scan chains or targets
features a comprehensive graphical user environment for ScanMaster setup and run-time control. Through the ScanNavigator RTE, ScanMaster executes boundary scan test and on-board programming routines and can easily be set up to perform conditional looping and branching operations – a critical feature for program debug and execution of diagnostic routines. ScanMaster can also be controlled through DLL calls using test executives such as National Instruments’ TestStand and Teradyne’s TestStudio, or through direct API access with language-based programming.