Boundary Scan (JTAG) Test Using Teradyne’s Di-Series and Teradyne’s High Speed Subsystem (HSSub)
Acculogic’s ScanNavigator boundary scan test environment, presents an easy, cost effective, and a robust way to perform boundary scan (JTAG) test and programming using Teradyne’s Di-Series & Teradyne’s High Speed Subsystem (HSSub) digital test instruments.
The integration of ScanNavigator with the Teradyne Boundary Scan Runtime Library (TERBSR), which includes an application programming interface (API), provides access to the high speed communication channels on Teradyne’s digital test instruments.
Using these channels, ScanNavigator can communicate with the test access port (TAP) on a circuit board that is being tested. Furthermore, multiple boards can be tested simultaneously by defining the TAPs in the Instrument Definition File of ScanNavigator test environment.Advantages of using Acculogic’s ScanNavigator with Terdayne’s digital instruments:
- No need to purchase additional hardware
- Significant reduction of tests costs & test times
- Quick deployment with large scale ATE systems
- Use tests developed in product design stage throughout the product life cycle – from design to prototype to manufacturing to repair & maintenance
ScanNavigator is a fully integrated boundary scan test environment that harnesses the power of Acculogic’s comprehensive set of boundary scan test and on-board device programming tools in a single, intuitive graphical user environment. Whether it’s high fault coverage shorts and opens testing on boundary scan nets, or programming PLDs and flash memory via the scan chain, ScanNavigator provides easy access to all the hardware and software tools necessary to develop, execute and diagnose boundary scan tests.
Teradyne Di-Series is a family of C-size VXI digital test instruments, with 64 (single-ended) or 32 (differential-pair) programmable channels per card, data rates up to 50 MHz and the flexibility, performance and ease of use to test all levels of integration from SRA/SRU to WRA/LRU.
Teradyne High Speed Subsystem is comprised of an 18-slot PXIe Express (PXIe) 3U Chassis with a bandwidth of nearly 1 GB/s between instruments. APXIe subsystem-timing controller provides precise sub-nanosecond inter-slot coordination. The Foundation includes a fast, dedicated Quad-Core computer running a 64-bit version of Windows 7, providing the LXI communication to the teststation host computer and integration with HSSub Core Instruments via the high bandwidth, low latency PXIe backplane.